Direct Mapping of Strain in a Strained Silicon Transistor by High-Resolution Electron Microscopy

Abstract

Aberration-corrected high-resolution transmission electron microscopy (HRTEM) is used to measure strain in a strained-silicon metal-oxide-semiconductor field-effect transistor. Strain components parallel and perpendicular to the gate are determined directly from the HRTEM image by geometric phase analysis. Si80Ge20 source and drain stressors lead to uniaxial compressive strain in the Si channel, reaching a maximum value of -1.3% just below the gate oxide, equivalent to 2.2 GPa. Strain maps obtained by linear elasticity theory, modeled with the finite-element method, agree with the experimental results to within 0.1%.