Abstract
This paper presents a digitally controlled oscillator (DCO) with a low-complexity circuit structure that combines multiple delay circuits to achieve a high timing resolution and wide output frequency range simultaneously while also significantly reducing the overall power consumption. A 0.18 µm complementary metal–oxide–semiconductor standard process was used for the design, and measurements showed that the chip had a minimum controllable timing resolution of 4.81 ps and power consumption of 142 µW with an output signal of 364 MHz. When compared with other designs using advanced processes, the proposed DCO demonstrated the best power-to-frequency ratio. Therefore, it can output a signal at the required frequency more efficiently in terms of power consumption. Additionally, because the proposed DCO uses digital logic gates only, a cell-based design flow can be implemented. Hence, the proposed DCO is not only easy to implement in different processes but also easy to integrate with other digital circuits.
Highlights
In digital chips, all circuits rely on clock signals for signal synchronization and coordination to ensure correct timing and functional operation
The main (DCDE), we focus on the design of digitally controlled delay element (DCDE) in the review of digitally controlled oscillator (DCO) architecture
The proposed DCO was designed through the cell-based design flow and implemented according to the TSMC 0.18 μm 1P6M CMOS standard process
Summary
All circuits rely on clock signals for signal synchronization and coordination to ensure correct timing and functional operation. The ADPLL operates as follows: the compares the phases and frequencies of the input reference clock signal and the feedback. Because the output jitter represents the frequency stability of the generated clock signal. The jitter of the ADPLL is related to the operating environment and locking algorithm of the chip but is affected by the timing resolution of the DCO. When the timing resolution is high, changing the DCO digital control code changes has less of an effect on the output signal frequency, which reduces the jitter. DCDEisistotocontrol controlthe thedriving drivingcurrent current circuit loading digital condesign concept oror circuit loading byby digital control trol code to obtain different delay times and generate different output periods.
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