Digital Realization of Blind Extraction for Bit Synchronized Clock of Digital Signal with Any Duty Cycle

Abstract

This paper proposes a dual-core digital system which is designed by using field programmable gate array (FPGA) and digital signal processing (DSP). The system applies software algorithm to realize automatic identification of digital signal with arbitrary duty cycle and wide range of blind extraction of synchronous clock. At the same time, according to the principle of two-way dotting, the reason causing the error of blind extraction bit synchronous clock frequency is analyzed in detail, and the formulas of relative error and maximum relative error of blind extraction frequency of two-way dot are summarized. The formulas have theoretical guidance and practical significance for all two-way dot systems. Through the test, by using 150MHz clock, frequency tracking in blind synchronization can be realized for the single-polarity not-return-to-zero digital signal below 12Kbps. The experimental data show that for the same rate of unipolar not-return-to-zero code (NRZ) and unipolar return-to-zero code (RZ) with duty cycle D , the relative error of blind extraction frequency of RZ is 1/(D, 1 − D)min times that of NRZ. The experimental results show the validity of the relative error formulas of blind extraction frequency.