Digital predistorters sensitivity to delay alignment resolution

Abstract

In this paper, the effects of delay alignment between power amplifiers' input and output waveforms used to synthesize the digital predistorters (DPD) is discussed. Various delay values are applied to align the input and output waveforms; and a memory polynomial based DPD model is synthesized for each delay value. Then, the effects of the residual delay on the performance of the linearized amplifier are evaluated. This reveals that the DPD performance is altered by delay under-estimation. Conversely, the DPD is not sensitive to delay over-estimation by up to one sampling period. This overcomes the need for the signal up-sampling required for sub-sample fine resolution delay alignment, and considerably reduces the computational complexity of the digital signal processing algorithm employed for delay estimation and alignment. A low complexity coarse delay estimation and alignment algorithm is then proposed.