DIGITAL PID DESIGN FOR MAXIMALLY DEADBEAT AND TIME-DELAY TOLERANCE

Abstract

This paper presents a new approach to design a digital PID controller for a given LTI plant. By using the Tchebyshev representation of a discrete time transfer function and some new results on root counting with respect to the unit circle, we show how the digital PID stabilizing gains can be directly obtained by solving sets of linear equations. This solution is attractive because it determines the entire set of stabilizing PID gains constructively if exists, Using this characterization of the stabilizing set, we present solutions to two design problems: a) Maximally dead beat design where we determine the smallest circle within the unit circle wherein the closed loop characteristic roots may be placed by PID control, b) Maximal delay tolerance-where we determine the maximal loop delay that can be tolerated under PID control.