Digital Phase-Locked Loop

Abstract

One of the most challenging tasks in analog circuit design is to adapt a functional block to ever-new CMOS process technologies. For digital circuits, the number of gates per square milimeter approximately doubles per chip generation. Integration of analog parts in recent deep submicron technologies is much more difficult and additionally complicated because the usable voltage ranges are decreasing with every new integration step. The continued progress in increasing performance, speed, reliability, and the simultaneous reduction in size and cost of integrated circuits (LSI and VLSI) has resulted in a strong interest in implementation of the phase-locked loop (PLL) in the digital domain. In this chapter an overview of the Digital Phase-Locked-Loop (DPLL) system architecture is presented. An introduction to the operation is given, considering each of the DPLL components individually. The discrete time mathematical models of the various components of DPLL are discussed. Finally, the chapter ends with notes on classification of DPLL based on phase detection techniques, operational principles of various types of phase detector are also discussed.