Abstract
Binary multiplication is one of the fundamental arithmetic operations, and it is used in digital filters and signal processing applications. The Continuous Valued Number System (CVNS) is a recently introduced number system that allows digital arithmetic, with arbitrary precision, to be implemented with analog circuitry. Due to the analog nature of the numbers system, CVNS reduces the total system and cross talk noise. An <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8×8</i> digital multiplier is proposed, using CVNS compressors for reducing the digital partial products. A new definition for the CVNS compressor for the first time is introduced, along with a novel CMOS current mode circuit. The multiplier is realized in TSMC CMOS <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.18μm</i> technology, with a maximum delay of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">900ps</i> , static power consumption of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19mW</i> and a core area of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11200μm<sup>2</sup></i> . The example demonstrates that CVNS designs can yield fast, low power arithmetic circuits using low noise analog circuitry.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callSimilar Papers
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
