Abstract
In this work, a novel digital leaky integrate-and-fire neuron design is proposed as part of a charge-trap transistor (CTT)-based neuromorphic system. CTTs, which are compute-in-memory devices, are used to realize the synaptic array of the neuron and support weight multiplication operations for incoming pulse signals. The proposed digital neuron does not rely on a capacitor for accumulation, making it area-efficient and scalable, and thus useful for design of large spiking neural networks. The neuron accumulates the weighted inputs from the synaptic array and generates an outgoing pulse, i.e., fires, when a pre-set threshold is reached. The digital neuron includes a sampler circuit, multi-level comparator, pulse generator, leaky circuit, 3-bit counter, and digital comparator circuit. Since the circuit is digital, the design is robust to noise, mismatch, and process, voltage, and temperature variations. The digital neuron is designed in GF 22 nm FDSOI technology, operates at a supply voltage of 0.8 V, and occupies an area of 33.5 μ m2. The neuron was simulated, including under temperature and supply voltage variations, and exhibits expected functionality.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.