Digital in‐situ biasing technique

Abstract

A highly digital in-situ biasing solution for analogue interfaces in nanoscale complementary metal-oxide semiconductor (CMOS) technologies is presented. The digital biasing scheme uses a time-based successive approximation conversion to provide the desired analogue functions with the voltage/current input and output. The digital biasing circuit obtains benefits from scaled devices with a small dimension and a high Ft, but with no design difficulties by the advanced CMOS process. By taking advantage of ultra-compact digital logic for control and adaptation, the digital biasing circuit does not suffer from the impact of intra-die variations since it eliminates the need for shared biasing approaches. A digital common-mode feedback circuit (CMFB) for a fully differential amplifier was simulated to demonstrate the advantages of the digital in-situ biasing scheme. The digital CMFB designed in a 65 nm CMOS process provides a desired output common-mode voltage as a conventional analogue CMFB, but does not need any stability compensation schemes. Compared with the analogue CMFB, the digital CMFB with the digital-like structure is more robust, has much smaller area, and does not require large passive components.