Digital ground bounce reduction by phase modulation of the clock

Abstract

The digital switching noise that propagates through the chip substrate to the analogue circuitry on the same chip is a major limitation for mixed-signal SoC integration. In synchronous digital systems, digital circuits switch simultaneously on the clock edge, hereby generating a large ground bounce. In order to reduce the spectral peaks in the ground bounce spectrum, we combine the two techniques: (1) phase modulation of the clock; and (2) introducing intended clock skews to spread the switching activities. Experimental results show around 16 dB reductions in the spectral peaks of the noise spectrum when these two techniques are combined. These two techniques are believed to be good candidates for the development of methodologies for digital low-noise design techniques in future CMOS technologies.