Digital compensation of analog circuit imperfections in a 2-stage 6th order Σ–Δ modulator

Abstract

This paper presents a method to digitally correct for static, analog circuit imperfections in a two-stage, 6th order, cascaded sigma–delta modulator. By adding a digital correction term to the output of the digital noise cancellation filter, the first stage parasitic quantization noise due to finite amplifier gain and C-ratio mismatches can be completely removed. This enables operation without significant degradation for amplifier gains as low as 400 at OSRs ranging from 16 to 24. Measurements have been conducted with a prototype circuit to verify the proposed error correction technique. The experimental results are in good agreement with the theoretical expressions and simulations.