Digital communication in VLSI design

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With advances in VLSl design. clock sped in digital system designs are increasing in relation to propagation delays. This is causing increasing problems with the traditional synchronous design mcthodologies, cenaidy at the system and board levels, and increasingly even within high performance chips. Because of this problem, and other facton such as limitations in the number of pins in each package, interconnect and communications within a digital system is often a fundamental limitation to system performance. This is especially true in same signal pmcessing applications. where the amount of computafian per sample value is relatively small. and hence the system is often VO bound rather than pmcessing bound. Since pmcessing power is generally increasing faster than U0 resources for existing packaging technologies, U0 will become a bottleneck in an increasing number of applications. Pmblems such as large pmpagation delay have been faced since the earliest days of digital Communication system design, and hence there are a number ofoppRur&3es to apply digital communications principles to VLSI and digitaI system design. In this paper. we discuss some of these oppo!iunities