Digital Block Defect Localization using in-depth Circuit Analysis for Electrical Verification and Fault Isolation Correlation

Abstract

Defect localization on a digital block is challenging, since modern gate densities makes in-circuit micro-probing to do voltage mapping almost impossible. Additionally, large top metal layer areas often preclude the use of top-side analysis to validate a fault isolation result. However, with in-depth circuit analysis, the correlation between electrical failure mode and fault isolation result can be established, which facilitates identification of the most probable defective node within the faulty block. Further fault localization techniques, such as curve trace micro-probing and OBIRCH analysis, perform a vital role in identifying the defect location. A case study is presented to demonstrate that the failure mechanism can be successfully determined using these techniques.