Digital back-propagation ASIC design for high-speed coherent optical system

Abstract

We analyze the performance limits of the digital back-propagation (DBP) algorithm implemented in application specific integrated circuits (ASIC). The proposed hardware implementation, jointly with a set of other digital signal processing (DSP) blocks, was experimentally evaluated by processing a 32 GBd PDM-16QAM signal. In the transmitter side, it is discussed the linear filters complexity for Nyquist spectral shaping and the trade-off between number of taps and filter roll-off. Then, at the receiver, linear filters and nonlinear compensators are used to equalize chromatic dispersion (CD) and nonlinear distortions, respectively. These stages characterize the DBP block, which is able to enhance the transmission reach and the optimum launch power of the optical system. Transmission performance is optimized for different DBP implementations, considering two CMOS technology nodes: 16 nm and 28 nm. The DBP complexity is evaluated in terms of the required die size and in terms of number of the DBP stages and fiber span-lengths. For a target gain of 35% (in comparison with the CD-only compensation) on the transmission reach, the required DBP chip size is around 1.6 mm x 1.6 mm using 16 nm CMOS technology. The chip area of the nonlinear stage is only 16% larger than the linear stage.