Digital Assisted Truncation Noise Shaping Technique for Multi-bit $$\Sigma \Delta $$ Modulators

Abstract

A second-order multi-bit $$\Sigma \Delta $$ modulator facilitating the usage of a two-step flash analog-to-digital converter (ADC) as an internal quantizer is presented. A digital assisted low-resolution feedback digital-to-analog converter (DAC) is introduced containing digital sigma-delta modulators (DSDMs) to reduce the number of levels in the feedback DAC alleviating dynamic element matching requirements. Two-step flash ADC as an internal quantizer in a $$\Sigma \Delta $$ modulator provides higher resolution; however, the delay in the two-step ADC can introduce instability in the $$\Sigma \Delta $$ modulator loop. In the proposed architecture, the fast processing of the digital integrator of DSDM in the feedback path compensates the latency of the two-step flash ADC. Therefore, this architecture provides more than 6 bits of resolution in the internal quantizer. The implementation of an extra DSDM in the outermost feedback path relaxes the matching requirement of the analog and digital integrators. The effectiveness of the proposed structure is demonstrated by the study of nonlinearities of the analog integrators.