Abstract

Three-dimensional (3D) integration technology using Cu interconnections has emerged as a promising solution to improve the performance of silicon microelectronic devices. However, Cu diffuses into SiO2 and requires a barrier layer such as Ta to ensure acceptable reliability. In this paper, the effects of temperature and strain normal to the interface on the inter-diffusion of Cu and Ta at annealing conditions are investigated using a molecular dynamics (MD) technique with embedded atomic method (EAM) potentials. Under thermal annealing conditions without strain, it is found that a Cu-rich diffusion region approximately 2 nm thick is formed at 1000 K after 10 ns of annealing. Ta is capable of diffusing into the interior of Cu but Cu hardly diffuses into the inner lattice of Ta. At the Cu side near the interface an amorphous structure is formed due to the process of diffusion. The diffusion activation energy of Cu and Ta are found to be 0.9769 and 0.586 eV, respectively. However, when a strain is applied, a large number of crystal defects are generated in the sample. As the strain is increased, extrinsic stacking faults (ESFs) and lots of Shockley partial dislocations appear. The density of the dislocations and the diffusion channels increase, promoting the diffusion of Cu atoms into the inner lattice of Ta. The thickness of the diffusion layer increases to 4 times the value when only a temperature load of 700 K is applied. The MD simulations demonstrated that Ta is very effective as a barrier layer under thermal loading only, and its effectiveness is impaired by tensile strain at the Cu/Ta interface. The simulations also clarified the mechanism that caused the impairment. The methodology and approach described in this paper can be followed further to study the effectiveness of barrier layers under various annealing and strain conditions, and to determine the minimum thickness of barrier layers required for a particular application.

Highlights

  • Three-dimensional (3D) integration technology using Through-Silicon-Via (TSV) interconnections has emerged as a promising solution to improve the performance of silicon microelectronic devices

  • As Cu can rapidly diffuse into Si and SiO2 and cause reliability issues that are related to the loss of their insulation function, a barrier layer is mandatory between Cu and the surrounding dielectrics.[4]

  • A linear relationship exists between the diffusion thickness and the square root of the annealing time, indicating that the evolution of interfacial morphology is controlled by diffusion.[24]

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Summary

Introduction

Three-dimensional (3D) integration technology using Through-Silicon-Via (TSV) interconnections has emerged as a promising solution to improve the performance of silicon microelectronic devices.

Methods
Results
Conclusion

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