Abstract

The extension of optical lithography to 32nm and beyond is made possible by Double Patterning Techniques (DPT) at critical levels of the process flow. The ease of DPT implementation is hindered by increased significance of critical dimension uniformity and overlay errors. Diffraction-based overlay (DBO) has shown to be an effective metrology solution for accurate determination of the overlay errors associated with double patterning [1, 2] processes. In this paper we will report its use in litho-freeze-litho-etch (LFLE) and spacer double patterning technology (SDPT), which are pitch splitting solutions that reduce the significance of overlay errors. Since the control of overlay between various mask/level combinations is critical for fabrication, precise and accurate assessment of errors by advanced metrology techniques such as spectroscopic diffraction based overlay (DBO) and traditional image-based overlay (IBO) using advanced target designs will be reported. A comparison between DBO, IBO and CD-SEM measurements will be reported. . A discussion of TMU requirements for 32nm technology and TMU performance data of LFLE and SDPT targets by different overlay approaches will be presented.

Highlights

  • 193nm optical immersion lithography is approaching its minimum practical single-exposure limit of 80nm pitch [1]

  • The multi-pad empirical diffraction-based overlay technique is capable of controlling the overlay in double patterning optical lithography processes (DPT)

  • The usable range of LELE double patterning technology (DPT) empirical diffraction-based overlay (eDBO) is ±70nm. eDBO results agree well with traditional image-based overlay (IBO) results and with overlay calculated from CD-SEM data

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Summary

Introduction

193nm optical immersion lithography is approaching its minimum practical single-exposure limit of 80nm pitch [1]. The International Technology Roadmap for Semiconductors (ITRS) [2] target for overlay control at the 32nm DRAM node in single patterned lithography steps is 6nm. The freezing material prevents the first resist layer from washing away during the second layer PEB and develop steps The spacer lithography technique has most frequently been applied in patterning fins for FinFETs and metal layers [5] These pitch splitting double patterning techniques involve more demanding process steps, they require tighter overlay control than conventional single patterning [2]. Kandel et al [11] used arrays of specially constructed pads with programmed offsets to determine overlay without the need for model fitting These DBO methods have the potential to meet the demanding overlay metrology budget for sub-32nm technology nodes. The advantages of DBO for precise and accurate overlay measurement in LELE, LFLE and SADP processes will be shown

Spectroscopic scatterometry
Spacer double patterning
Findings
Conclusion
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