Abstract
A Pulse-Amplitude-Modulated Differential-Time-Signaling (PAM-DTS) Architecture for serial communication links is presented in this paper. The proposed link utilizes multi-level pulse-amplitude modulation (PAM) as-well-as multi-level pulse-position modulation (PPM) of the rising and the falling edges of the input clock signal, and uses one transmission channel to transmit the data as well as the clock. Applying the amplitude modulation to the DTS transmitted signal efficiently increases the link rate without significantly affecting the signal bandwidth. A 65nm CMOS example of a 6-bit 9Gb/s PAM-DTS link has been designed and simulated using 1.5GHz as an input clock signal. The simulated power consumption of the transmitter and the receiver combination is less than 22mW.
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