Abstract
An integrated differential two-stage power amplifier (PA) operating at the 2 GHz frequency range is introduced. The implemented power amplifier uses 2.7 V supply voltage and was fabricated with 0.35/spl mu/m SiGe BiCMOS technology. The measured output power at the -1 dB compression point is 21 dBm, but the amplifier is capable of providing 26.7 dBm output power at the -5 dB gain compression. The measured linear gain is 22 dB. The chip area is 2.36 mm/sup 2/ including bonding pads. The linearity performance of the power amplifier was measured with 3GPP WCDMA basestation signal. The power amplifier fulfilled the 3GPP WCDMA Adjacent Channel Leakage Ratio (ACLR) specifications (ACLR1=45 dB and ACLR2=50 dB) with 11.65 dBm average channel output power.
Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
