Differential clock cross-point correction method for pipeline ADCs

Abstract

Differential clock cross point correction method is presented in this paper. The proposed method provides differential clock with minimum crossing error over PVT, which is needed to improve noise immunity of Pipeline ADC. As Pipeline ADC work with differential clock, so crossing error of differential clock could decrease noise immunity. Cross point correction method also helps to avoid setup/hold violations in some systems. Proposed architecture can be used in different architecture of Pipeline ADCs, in the special input/output circuits of several standards such as Universal Serial Bus (USB) Peripheral Component Interconnect (PCI) and Double Data Rate (DDR).