Abstract
The voltage dependence of the high-frequency capacitance of a metal-ferroelectric-insulator-semiconductor (MFIS) structure is analyzed by relating the potential profile to the dielectric hysteresis of the ferroelectric thin film. About one hundredth of the dielectric polarization of ferroelectric ceramic PZT is enough to control the Si surface potential for ferroelectric gate FET memory, and large coercive force is required to obtain enough voltage window. MFIS structures using Bi-layer-structured ferroelectric thin films are also studied from experimental viewpoint. SrBi 2Ta 2O 9 and Bi 4Ti 3O 12 thin films have been prepared by laser ablation method on both Pt sheet and Si wafers at low temperatures of 400–500°C. SrBi 2Ta 2O 9 thin films have a good (105) preferential orientation, and Bi 4Ti 3O 12 thin films have (117) and c-axis orientations on these substrates. D-E hystereses are obtained in SrBi 2Ta 2O 9 and Bi 4Ti 3O 12 thin films prepared on Pt sheet, and are enough to control the Si surface potential. Ferroelectric film-SiO 2Si structures show good C–V hysteresis curves owing to the Si surface potential controlled by the D-E hysteresis.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
