Abstract

In the fast- paced semiconductor industry the need for package solution arises in order to cope with emerging miniaturization trend. As wafer thickness decreases to 100 μm and below, manufacturing challenges arise. Ultra-thin wafers are less stable and more vulnerable to stresses, and the die can be prone to breaking and warping not only during grinding but also at subsequent processing steps.Thinner dies will be able to perform faster heat dissipation to the Cu leadframe to improve the Rth and at the same time will be able to improve the Rdson performance. An effort to assemble an Ultra Thin Dies has been made at die bonding using soft solder, solder paste and also Au Sn Diffusion Soldering. This paper discusses the process optimization and challenges being done at die bond process by using multi needles and peel and ramp concept in order to pick and place such a thin dies in the range of chip thickness less than 60 um . Challenges such as die warpage has been minimized by optimizing the impact of vacuum suction during pick and place on the ultra thin wafer since thin die is very flexible and will be very much influence by the vacuum suction force. The other key parameter is the design of the collect vacuum holes which induced the suction force across the chip surface and will influence its stability during pick and place. The two concepts of pick and place using multi needles and peel and ramp have its own advantages and disadvantages. The experiments conducted revealed the capability of the multi needles and peel and ramp and for stable production both concept works in certain chip sizes with its own process limitation. A feasibility study on ultra thin wafer thickness during pick up and assembly process shows the concept used at die bonding can reduces the stress impact exerted on the chip during pick and place with a proper design of die bonding collet, reduction of die warpage and effect of vacuum suction during pick up process. However in order to achieve a stable production a lot of efforts still need to be done and it involves process optimization , die bonding equipment control and front end wafer technology side.

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