Dichotomy-based model for FSM power minimization

Abstract

Switching activity and capacitive load both affect power consumption in VLSI circuits. In two-level logic implementations, due to the regular structure, more information about the find implementation is available at an early stage. In order to optimize power during the state encoding step in the synthesis of finite state machines (FSMs), both capacitance and switching activity need to be considered. Most of the previous work does not consider accurate measures of both capacitance and switching activity on all nodes in the circuit simultaneously. We propose a new approach based on the concept of dichotomy, to find accurate measures for both switching activity and capacitive load on all nodes in two-level implementations of FSMs from their symbolic specification. The area of the resulting implementation can also be measured in the proposed model. Experimental results on MCNC benchmarks indicate the effectiveness of our approach in reducing the power consumption. The areas of the resulting implementations are also reduced in almost all the cases, indicating that power and area are strongly related in two-level implementations.