Diamond-Shaped e-SiGe Optimization by TCAD Simulation to Improve P-type MOSFET Performance for 28nm Logic Technology and Beyond

Abstract

The embedded-SiGe (e-SiGe) stressor has been an indispensable p-channel MOSFET (pFET) performance booster in the advanced logic technology nodes. In this work, we did extensive study by TCAD simulation on the optimization of the tip location, the Ge concentration profile, the in-situ doped B concentration profile of the diamond-shaped e-SiGe stressor. We observed that a shallower and closer-to-channel e-SiGe tip, higher overall Ge concentration, and faster Ge concentration ramp-up rate starting from the Si/e-SiGe interface could increase compressive stress and therefore improved the device Ion/Ioff by hole mobility enhancement. The in-situ doped B concentration profile needs to be optimized to avoid short channel effect (SCE) degradation while reducing Rext. A relatively low in-situ B concentration at Si/e-SiGe interface and a high in-situ B concentration in the “bulk” SiGe are desired. On the other hand, the e-SiGe overfill height and the e-SiGe profile at the diffision/STI boundry also play an important role in the pFET performance. The above findings serve as useful references for the e-SiGe stressor optimization for the 28nm logic technology node and beyond.