Diameter Scaling of Vertical Ge Gate- All-Around Nanowire pMOSFETs

Abstract

In this article, vertical Ge gate-all-around (GAA) nanowire pMOSFETs fabricated with a top–down approach are demonstrated. Thanks to optimized dry etching and digital etching, high-performance Ge GAA nanowire pFETs show low subthreshold swing (SS) of 66 mV/dec, small DIBL, and ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of $> 10^{{6}}$ . The impact of nanowire diameter scaling from 65 to 20 nm on the key electrical figures of merit (FOMs) of vertical nanowire devices is investigated. The devices with 65-nm diameters show the highest ${I}_{ \mathrm{\scriptscriptstyle ON}}$ and peak transconductance ${G}_{\text {max}}$ due to reduced total resistance $R_{\text {tot}}$ , while the smallest diameter devices yield the largest ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratios and the smallest DIBL due to strong gate electrostatics. The source/–drain asymmetry inherently exists in the vertical nanowire architectures. By swapping the source and drain, electrical FOMs keep the similar trend in diameter scaling. ${I}_{ \mathrm{\scriptscriptstyle ON}}$ , ${R}_{\text {tot}}$ , and ${G}_{\text {max}}$ asymmetry can be attributed to top–bottom contact resistance difference resulting from the doping deactivation effect in small nanowires.