Diagnostic Test Generation for Transition Delay Faults Using Stuck-At Fault Detection Tools

Abstract

By adding a few logic gates and one or two modeling flip-flops to the circuit under test (CUT), we create a detection or diagnostic automatic test pattern generation (ATPG) model of transition delay faults usable by a conventional single stuck-at fault test pattern generator. Given a transition delay fault pair, the diagnostic ATPG model can either find an exclusive test or prove the equivalence of the fault pair. Our work offers advantages over existing work. First, the detection of a transition delay fault or the diagnosis of a fault pair can be modeled in only one instead of two or four time-frames of the CUT. Second, an exclusive test can be generated under either launch off capture (LOC) or launch off shift (LOS) mode for a full-scan sequential circuit. Third, the proposed ATPG models can be expanded into two time frames to facilitate the use of combinational ATPG tools, though with lower modeling complexity than was possible before. As a result, the percentage of distinguished transition delay fault pairs is larger and the proposed automatic exclusive test generation system is more time-efficient.