Abstract
We present a Built-in Self Test (BIST) methodology for on-chip failure analysis of via/contact voiding due to electromigration (EM) and stress-induced voiding (SIV) in SRAM cells. Our BIST system detects wearout and identifies the location of the worn out via in the cell By matching the observed failure rate from BIST and the failure distribution function based on mathematical models, we can identify the cause of failure and potentially distinguish EM and SIV failures. Hence, the method determines separate wearout distributions for EM vs. SIV with electrical tests only.
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