DfT techniques for first-time right MCMs-exemplified by a Pentium MCM system

Abstract

The controllability and observability aspects of MCM test must be considered at a very early design stage, which is widely known as design for testability (DfT). In order to demonstrate the advantages of DfT strategies for complex MCM designs, the Electronics Laboratory of the Swiss Federal Institute of Technology in Zurich has developed a thin film MCM-D which incorporates a Pentium processor with associated chip set and memory (512 kbyte of second level cache). This means that different test structures (and underlying DfT philosophies) of commercially available chips, like BIST, boundary-scan and NAND trees, had to be combined with chips for which none of these structures are available. The challenge for such a design is to develop the most effective and, especially, cost-effective DfT strategy that allows testing of an MCM to the same level as packaged components, as well as providing quick and accurate fault localization to allow rework in the manufacturing process. The paper briefly introduces the demonstrator MCM, and gives an overview of the different structures utilized. The main focus of the paper is, however, placed on the implementation of the DfT technologies actually used in the MCM design by identifying and analyzing the different options. This was done using a consequent top-down methodology to manage the complexity of this processor based MCM. The paper then presents, discusses and evaluates real test results obtained on the Electronic Laboratory's industrial HP83000 F330t test system and draws conclusions about the effectiveness of the approach.