DfT support for launch and capture power reduction in launch-off-capture testing

Abstract

At-speed or even faster-than-at-speed testing of VLSI circuits aim at a high quality screening of VLSI circuits by targeting performance-related faults. On one hand, a compact test set with highly effective patterns, each detecting multiple delay faults, is desirable to lower test costs. On the other hand, such patterns increase switching activity during launch and capture operations. Patterns optimized for quality and cost may thus end up violating peak power constraints, resulting in yield loss, while pattern generation under low switching activity constraints may lead to loss in test quality and/or pattern count inflation. In this paper, we propose DfT support for enabling the use of a set of patterns optimized for cost and quality as is, yet in a low power manner. The DfT support we outline in this paper enables a design partitioning approach, where any given set of patterns, generated in a power-unaware manner, can be utilized to test the design regions one at a time, reducing both launch and capture power in a design flow compatible manner. This way, the test pattern count and quality of the optimized test set can be preserved, while lowering launch/capture power.