Device-saving pipeline architectures of multi-dimensional DCT similar butterfly algorithm

Abstract

In traditional multi-dimensional discrete cosine transform (DCT) algorithm, n dimensions are processed separately. In order to realize n-D global DCT and construct the unity architectures of blocks with different sizes, we have proposed n-D DCT similar butterfly algorithm and its unit pipeline architectures. And in order to solve the problems of this algorithm hardware architectures use a lot of delayers or selectors independently and in algorithm different blocks are not easy to integrate, based on the basic principles of DCT and on the basis of the “tensor” operation, premised on the multi-dimensional DCT pipeline algorithm we have proposed, we invest algorithm architectures to save devices. Firstly, we present n-D DCT pipeline algorithm based on theory of 1-D DCT and tensor product operation in brief, and give n-D DCT similar butterfly architectures. Secondly, we propose pipeline architectures units and the corresponding whole pipeline architecture of n-D DCT. Thirdly and foremost, we set up delayers-group models by reusing delayers and selectors, the models are integrative and nested. The experimental results indicate that the reduce ratio of number of delayers and selectors increased obviously as block size increase by using our device-saving algorithm. The characteristics of our pipeline architectures algorithm are fast, low complexity, and multidimensional compatibility.