Device Performance Improvement of PMOS Devices Fabricated by $\hbox{B}_{2}\hbox{H}_{6}$ PIII/PLAD Processing

Abstract

It has been shown that plasma immersion ion implantation (PIII)/plasma doping (PLAD) processing offers unique advantages over conventional beam-line ion implant systems, including system simplicity, lower cost, higher throughput, and device performance improvements. A 78-nm channel length PMOS device, which is fabricated by a B <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> /H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> PIII/PLAD process on source/drain doping, can offer better device performance that includes a 50% lower contact resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CS</sub> ), 11%-16% higher drive current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> ), and transconductance (KL) than those fabricated by beam-line implantation. The physical mechanisms behind the device performance improvement can be correlated to the much lower R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CS</sub> , which in turn results from the unique dopant profiles of the PIII/PLAD process.