Device optimization and performance of 3.5 cm<sup>2</sup> silicon SGTO for Army applications

Abstract

The U.S. Army Research Laboratory (ARL) has been investigating silicon super gate turn-off thyristors (SGTOs) for high action pulse switching necessary for Army survivability and lethality applications. The silicon SGTO designed by Silicon Power Corporation (SPCO) was evaluated to determine its repeatable pulse current capability at a 1 ms pulse width. The initial SGTO design was a 3.5 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip rated for 4 kV forward blocking and 10 kA peak current at 10 µs pulse width or 100 A continuous. The previous work by ARL on these switches reported repetitive peak current of 5 kA with a charge voltage of 4 kV. Additionally, the switches failed short at peak currents of 6 kA, with calculated action of 1.3 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> A <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> s at 5 kA. This work highlights the device optimization that SPCO has since made on the Si SGTO to improve the device pulsing performance. The latest Si SGTO evaluated maintains the same chip area and active area as the previous devices. Modification to the mask layout and the enhancement of the emitter design enables the latest Si SGTO to exhibit repeatable peak current of 5.5 kA (a 10% increase compared to the previous batch). The calculated action for the latest switches was 1.6 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> A <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> s at 5.5 kA.