Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications

Jun-Sik Yoon,Rock-Hyun Baek

doi:10.1109/access.2020.3031870

Jun-Sik Yoon, Rock-Hyun Baek

Open Access

https://doi.org/10.1109/access.2020.3031870

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Abstract

Analog/RF performances of 5-nm node bulk fin-shaped field-effect transistors (FinFETs) and nanosheet FETs (NSFETs) were investigated and compared thoroughly using fully-calibrated TCAD. NSFETs have greater current drivability and gate-to-channel controllability than FinFETs under the same footprint, thus achieving larger intrinsic gain. But the cutoff frequencies (F t ) of FinFETs and NSFETs are comparable due to larger gate capacitances (C gg ) of NSFETs compensating DC performance improvements. Gate resistances (R g ) of NSFETs are larger because of their metal gate (MG) configuration surrounding the channels, longer MG height by the top-most NS spacing region, and the bottom transistor, thus degrading maximum oscillation frequency (F max ). Device design guidelines of FinFETs and NSFETs are also studied for better intrinsic gain, F t , and F max . Intrinsic gain is improved by better electrostatics, whereas F t increases by greater current drivability over C gg . For larger F max , careful device design is required to compensate between R g , C gg , output resistance, and F t . Overall, NSFETs outperform FinFETs in terms of intrinsic gain, F t , and F max , thus NSFETs are promising for analog/RF applications.

Highlights

Si fin-shaped field-effect transistors (FinFETs) have been scaled down to 10-nm node through higher aspect ratio and layout optimization [1]
There is a cross-over of GmRo between nanosheet FETs (NSFETs) and FinFETs at small Ids near 10−7 A/μm because NSFETs have larger dopant penetration into the channel, which decreases the Ro
Large Rg,int including top-most NS spacing and bottom regions degrades the Fmax of NSFETs over FinFETs

Summary

INTRODUCTION

Si fin-shaped field-effect transistors (FinFETs) have been scaled down to 10-nm node through higher aspect ratio and layout optimization [1]. FinFETs started to substitute planar MOSFETs through design-technology co-optimization in terms of performance, power, and area for system-onchip applications [2]. Si nanosheet FETs (NSFETs) have been introduced to increase the channel effective widths (Weff) for greater current drivability under the same footprint while maintaining superior electrostatics through gate-all-around (GAA) structure [6]. FinFETs have substituted planar MOSFETs for analog/RF applications due to better electrostatics achieving high intrinsic gain (GmRo) and volume inversion lowering 1/f noise [9]–[11]. Analog/RF performances of NSFETs have been investigated in terms of NS channel thickness (TNS) and WNS for better analog/RF figure-of-merits (FoM) (GmRo, Ft , Fmax ) [14]. After structural analyses of FinFETs and NSFETs, device design guidelines for best analog/RF FoM were presented. Were analyzed and provided for the further study of non-linear and noise equivalent circuit models

DEVICE STRUCTURE AND SIMULATION METHOD

RESULTS AND DISCUSSION

CONCLUSION