Device Design and Scalability of a Double-Gate Tunneling Field-Effect Transistor with Silicon–Germanium Source

Abstract

A novel double-gate (DG) tunneling field-effect transistor (TFET) with silicon–germanium (SiGe) Source is proposed to overcome the scaling limits of complementary metal–oxide–semiconductor (CMOS) technology and further extends Moore's law. The narrower bandgap of the SiGe source helps to reduce the tunneling width and improves the subthreshold swing and on-state current. Less than 60 mV/decade subthreshold swing with extremely low off-state leakage current is achieved by optimizing the device parameters and Ge content in the source. For the first time, we show that such a technology proves to be viable to replace CMOS for high performance, low standby power, and low power technologies through the end of the roadmap with extensive simulations.