Device circuit co-design using classical and non-classical III–V Multi-Gate Quantum-Well FETs (MuQFETs)

Abstract

This paper presents ultra low-power reconfigurable logic and single-electron memory architecture to enable sub-300 mV V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CC</sub> operation using classical and non-classical (NC) III-V Multi-Gate Quantum Well Field Effect Transistors (MuQFETs). A strained In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.7</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.3</sub> As quantum-well based classical multi-gate FET and an In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.7</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.3</sub> As MuQFET operating in Coulomb-blockade mode with tunable tunnel barrier are experimentally demonstrated. Reconfigurable Binary Decision Diagram (BDD) logic and single-electron SRAM implementations based on III-V MuQFETs are demonstrated. Using device models well calibrated to experiments, we show 50% reduction in minimum-energy for logic, and 75× reduction in dynamic power for memory at equivalent performance over Si CMOS logic.