Abstract
A multi-nanosheet field-effect transistor (mNS-FET) device was developed to maximize gate controllability while making the channel in the form of a sheet. The mNS-FET has superior gate controllability for the stacked channels; consequently, it can significantly reduce the short-channel effect (SCE); however, punch-through inevitably occurs in the bottom channel portion that is not surrounded by gates, resulting in a large leakage current. Moreover, as the size of the semiconductor device decreases to several nanometers, the influence of the parasitic resistance and parasitic capacitance increases. Therefore, it is essential to apply design–technology co-optimization, which analyzes not only the characteristics from the perspective of the device but also the performance from the circuit perspective. In this study, we used Technology Computer Aided Design (TCAD) simulation to analyze the characteristics of the device and directly fabricated a model that describes the current–voltage and gate capacitance characteristics of the device by using Berkeley short-channel insulated-gate field-effect transistor–common multi-gate (BSIM–CMG) parameters. Through this model, we completed the Simulation Program with Integrated Circuit Emphasis (SPICE) simulation for circuit analysis and analyzed it from the viewpoint of devices and circuits. When comparing the characteristics according to the presence or absence of bottom oxide by conducting the above research method, it was confirmed that subthreshold slope (SS) and drain-induced barrier lowering (DIBL) are improved, and power and performance in circuit characteristics are increased.
Highlights
Semiconductor device technology has continued to develop rapidly in line with the rapidly developing information industry
We analyzed the change in characteristics caused by adding bottom oxide to the multi-nanosheet field-effect transistor (mNS-FET) device from the perspectives of the device and circuit
In the comparison according to the presence or absence of bottom oxide, it was confirmed that the subthreshold slope (SS), drain-induced barrier lowering (DIBL), and gate capacitance characteristics were improved for the device to which bottom oxide was added, and the leakage current and capacitor components were significantly improved when compared to the conventional device without bottom oxide
Summary
Semiconductor device technology has continued to develop rapidly in line with the rapidly developing information industry. The structure of FinFETs has reached its limit as the size of technology nodes has been reduced to less than 3 nm; it has become essential to develop a device having a gate-all-around (GAA) structure, which wraps all parts of the channel with a gate [4,5]. Such a structure maximizes the channel control capability of the gate. In this study, calibration was performed to extract parameter values to be used for accurate analysis of the channel portion and drift–diffusion simulation for multi-nanosheet field-effect transistor (mNS-FET) devices. Electronics 2021, 10, x FOR PEER REVI2E.WAnalysis of Characteristics According to the Presence or Absence of Bottom O3xiodfe
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