Development Write Performance by Enhancing Internal Parallelism of Solid State Drives

Abstract

Most research of Solid State Drives architectures rely on Flash Translation Layer (FTL) algorithms and wear leveling; however, internal parallelism in Solid State Drives has not been well explored. In this research, I proposed a new strategy to improve SSD write performance by enhancing internal parallelism inside SSDs. A SDRAM buffer is added in the design for buffering and scheduling write requests. Because the same logical block numbers may be translated to different physical numbers at different times in FTL, the on-board DRAM buffer is used to buffer requests at the lower level of FTL. When the buffer is full, same amount of data will be assigned to each storage package in the SSDs to enhance internal parallelism. To accurately evaluate performance, I use both synthetic workloads and real-world applications in experiments. I compare the enhanced internal parallelism scheme with the traditional LRU strategy, because it is unfair to compare an SSD having buffer with an SSD without a buffer. The simulation results demonstrate that the writing performance of our design is significantly improved compared with the LRU-cache strategy with the same amount of buffer sizes.