Development of variable-rate sequential decoder LSI

Abstract

A variable-rate soft decision sequential decoder LSI is described in detail. The decoder is more reliable and less expensive than a conventional Viterbi decoder, and thus can more effectively improve the performance of a very small aperture terminal. In implementing the decoder, the authors propose a metric replacing technique and a bit-serial decoding scheme. The former achieves quick restarting after a buffer overflow, replacing the metric of some parity bits with a predefined constant. The latter furnishes rate variability to the decoder, decoding a rate k/n code as a 1/1 code. Besides simplifying the implementation, it reduces the computational effort. With these and other techniques, the authors have succeeded in implementing the decoder on a CMOS gate array of 15 K usable gates. The decoder can be operated at any data rate up to 2 Mb/s. The code rate can be selected from among 1/2, 3/4, and 7/8. For R=1/2 code the decoder achieves 6.5 dB coding gain, which is superior to a K=7 Viterbi decoder by 1.0 dB at 10/sup -6/ output bit error rate and a 64 kb/s data rate. For R=3/4 and 7/8, the decoder exhibits significant superiority to the viterbi decoder at any data rate. >