Abstract

The nonlinear feedback shift registers of the second order inare considered, because based on them it can be developed a generator of stream ciphers with enhanced cryptographic strength. Feasibility of nonlinear feedback shift register search is analyzed. These registers form a maximal length sequence, using programmable logic devices. Performance evaluation of programmable logic devices in the generation of pseudo-random sequence by nonlinear feedback shift registers is given. Recommendations to increase this performance are given. The dependence of the maximum generation rate (clock frequency), programmable logic devices on the number of concurrent nonlinear registers is analyzed. A comparison of the generation rate of the sequences that are generated by nonlinear feedback shift registers is done using hardware and software. The author suggests, describes and explores the search method of nonlinear feedback shift registers, generating a sequence with a maximum period. As the main result are found non-linear 26, 27, 28 and 29 degrees polynomials.

Highlights

  • There is currently rapid development of cryptanalytic systems

  • nonlinear feedback shift registers (NLFSRs) on the basis of stream ciphers are included in Achterbahn [5], Dragon [6], Grain [7], Trivium [8] and VEST [9]

  • In this paper we study NLFSRs performance implemented on the field programmable gate arrays (FPGAs) and problems of their optimization

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Summary

Introduction

There is currently rapid development of cryptanalytic systems. One of the main requirements to the main element of the cryptographic stream encryption system – a generator of pseudorandom sequences (PRSs) is an indiscernible of the sequence, complexity, speed and repetition period for PRSs [1]. As has been shown in [25], the number of feedback coefficients aij for NLFSR with L size is calculated by ratio nL = L ⋅ (L + 1) / 2, n1 can take values in the range 0 ≤ n1 ≤ nL. The analytical method consists of checking the feedback coefficients to meet certain requirements as (2017), «EUREKA: Physics and Engineering» Number 1 detailed in [25, 26, 12]. For moving the computational process from CPU on the FPGA, performance (speed) of each of NLFSRs is maintained This fact allows to tens or hundreds of times increase the overall performance of the complex for M-NLFSR search compared to use only a PC.

Modification allowed to improve performance for
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Conclusions
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