Abstract
Technology scaling has revolutionized circuit configuration, permitting more than four billion transistors on a single chip. This capability enabled Electronic Design Automation (EDA) tools to be more complex. A chip must meet the timing constraints to operate at the expected clock rate. The Static Timing Analysis (STA) will validate whether the design could operate at the expected clock frequency, without any timing violations. This project represents the implementation of STA using Directed Acyclic Graph (DAG) of basic ISCAS'89 Benchmark circuit. The combinational critical path is being calculated using Floyd-Warshall Algorithm over Dijkstra's Algorithm and timing information and routing delay is given through the text file is PERL script. The violations can be solved by adding buffer, decreasing combinational delay, changing hold and setup time of the capture flip flops and by decreasing required operating frequency. Timing information and routing delay is given through the text file and then STA is performed using PERL script.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
