Development of Soft-Core Processor with Efficient Array Data Transfer Mechanism

Abstract

Recently, the use of FPGA in the fields of embedded systems has been increasing. However, there is a problem that it is difficult to develop dedicated circuit on FPGA in a short time in many cases. One method for solving this problem is to reduce the development cost of the dedicated circuit by migrating some part of the target task, whose performance is not critical in the system, onto soft-core processor. If the performance of the soft-core processor is improved, more part of the target task can be migrated onto it, the amount of the dedicated circuit to be developed can be further reduced, and thus the development cost can be reduced.However, when trying to raise the performance of soft-core processor, the improvement of the memory access performance is a critical issue, since the performance of memory system including off-chip memory is generally not high in embedded system. Therefore, in this paper, we aim to improve the performance of off-chip SDRAM memory access, and discuss the method of efficient data transfer that utilizes the SDRAM bandwidth as efficiently as possible. And we implement the mechanism to realize the efficient data transfer. We also develop a soft-core processor equipped with vector loading function as research prototype platform, and preliminarily evaluate the performance.