Development of Silicon Substrate for Advanced Multi-Chip Packaging Process with the Enhanced Gettering Ability

Abstract

Gettering techniques are the key features in recent semiconductor industry to develop the high performance devices. Above all, the intrinsic gettering is considered as the easiest way to achieve metal gettering effect in a silicon substrate with the formation of extended defects during thermal process. Moreover, intrinsic gettering is the only way available in the multi-chip packaging (MCP) technique that cannot be accompanied by the extrinsic gettering due to the backside grinding process [1]. Therefore, the epitaxial wafers based on the heavily boron-doped substrate have been used in MCP to obtain the gettering effect even in thinned substrate. However, the use of epitaxial wafers in the fabrication process leads the high cost of ownership (CoO) in the production. Thus, various investigations on the substitution of the epitaxial wafer have been carried out to reduce the total process cost. In this work, a novel concept of silicon substrate that represents the low-cost and comparable gettering efficiency on metal contamination to that of the epitaxial wafer was proposed. To achieve these features, rapid thermal annealing (RTA) adjusted at high temperature was applied to the base wafer with high interstitial oxygen (Oi) concentration. As shown in Fig. 1 a), oxygen precipitates was evenly formed over the entire bulk in the RTA-treated high Oi wafer after device heat simulation, which is favorable in thinned substrate for the MCP. In addition, the average size of oxygen precipitates increased in high Oi wafer, which means the ‘total inner surface’ of oxygen precipitates [2] was possibly expanded over the threshold value required for effective gettering. Finally, we confirmed the effect of RTA-treated high Oi wafer on the metal gettering after the thinning process, especially in nickel, which was more effective than in the epitaxial wafer up to 1.5 times while the gettering ability for copper was almost saturated in all wafer condition, as shown in Fig. 1 b). Specific features of our results will be discussed in detail. Fig. 1 a) Optical micrographs of entire bulk observed in RTA-treated wafers with different Oi level. Wafers were heat-treated and etched in the Wright etchant for 5 min. b) Gettering ability for copper and nickel contamination measured in RTA-treated samples after thinned to 30 μm thickness.