Development of reliable multilayer metallization for submicron ULSI technology

Abstract

Interconnect Research & Development, MS-J201LSI Logic Corporation, Santa Clara, CA 95054ABSTRACTIn this paper, various multilayer metallization schemes for 0.5 urn CMOS technology are studied.Experimental results show that multilayer interconnect consisting of A1Cu on Ti/TiN barrier layer hassuperior electromigration resistance as compared to that deposited on single TiN film. The application ofan advanced wafer-level reliability test enables us to investigate grain boundary diffusion controlled elec-tromigration phenomenon. The microstructural properties of the metallizations are also characterized byX-ray diffraction and Scanning Electron Microscope. The stress migration resistance is also studied usinghigh temperature storage at 175 °C and thermal cycle treatment at 450 °C.The study shows that the increase in (1 1 1) preferred orientation of AICu film and grain size with lessrandom distribution do improve the electromigration lifetime. The effects of various metal geometriessuch as interconnect width and thickness on reliability are also investigated in this paper. Data shows theelectromigration lifetime is not monotonically proportional to the increase in metal thickness. Due to thebamboo structure effect, the narrower interconnect shows the longer lifetime. An activation energy (Ba)of 0.94 eV is found for the multilayer metallization, TiTFiN/AICUJTiN. The resistance change measuredafter the stress migration experiment shows that the multilayer interconnect with the intermediate thick-ness of AICu has comparable stress migration resistance to those of thicker films. The effect of otherparameters like the thickness of TiN anti-reflective coating (ARC) on reliability is also investigated.