Development of post-CMP cleanup processing for Cu/low-k devices

Abstract

In recent years, Cu/low-k damascene (buried interconnects) processing, which uses Cu interconnects with low-dielectric-constant (low-k) films, has emerged as a way to satisfy the requirements for making devices ultrasmall, high-speed, and usable in ultralarge-scale integration (ultra-LSI). However, the use of Cu in combination with new materials to make the low-k films has led to difficulties in developing a process for cleaning after post-chemical-mechanical planarization (CMP). One of these problems is the presence of hydrophobic residuals on the low-k films, for whose removal many slurries (polishing agents) and cleaning fluids have been developed. In our work, we have combined these slurries and cleaning fluids, and investigated the effectiveness of the combinations in cleaning low-k films, allowing us to develop an optimum process. We determined the defect counts for TEOS, Cu, and two kinds of low-k films, and measured the level of contamination of the low-k film contaminant by spots of Cu, from which we identified cleaning fluid that performed best. We also confirmed that the performance of the cleaning fluids was different depending on the choice of slurry. We then used our optimum process to formulate a fabrication scheme for devices with the Cu/low-k structure, fabricated a set of devices, and investigated their electrical characteristics. Because of the significant reduction we observed in leakage currents between circuit lines to below 10−9 to 10−10A/m, we argue that our process can be used to fabricate ultra-LSI device ensembles under real conditions. © 2006 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 89(11): 19–30, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.20187