Development of multiprocessor system-on-chip based on soft processor cores schoolMIPS

Abstract

This work includes a review of MIPS architecture processor cores and a review of network topology consisting of routers. It was demonstrated by realization of 2 multiprocessor systems developed on the basis of mesh topology using modified schoolMIPS soft-processor cores, in which architecture additional blocks and instructions were added, and routers with XY routing. As a result, the obtained NoC performance is up to 1.87 Gbit/s (4 processor cores), and up to 1.54 Gbit/s (10 processor cores). The extended processor core schoolMIPS consumes 452 ALMs and 1692 bits of memory; NoC of 4 processor cores takes 2223 ALMs and 9136 bits of memory; NoC of 10 processor cores – 5696 ALMs and 22840 bits of memory. The obtained results suggest that there is a possibility of NoC development with the number of nodes up to 200 nodes on Stratix IV GX EP4SGX230 (DE4).