Development of Graphene Synthesis and Characterization Techniques toward CMOS Applications and Beyond

Abstract

Graphene exhibits mechanical and electrical properties which, coupled with its two dimensional (2D) morphology, make it an attractive material component for inclusion in a wide range of industries. Since the discovery of graphene in 2004, industry adoption has been limited due to the demanding synthesis requirements for high quality and connected graphene as well as the difficulties associated with direct incorporation. Chemical vapor deposition (CVD) has emerged as the most cost efficient method for producing high quality graphene at scales suitable for mass production. However, the 1000°C temperatures and micrometer thick catalysts required for this process preclude direct inclusion in applications with topographically varied surfaces as graphene is produced in planar sheets that must be transferred. One attractive application for graphene is as a diffusion barrier in CMOS applications as the single atom thick material has shown significant ability to block copper diffusion at elevated temperatures. For realization of this application, both the required catalyst thicknesses and synthesis temperatures for graphene production must be reduced to enable direct graphene incorporation on these nanoscale and nonplanar surfaces without thermal damage to existing components. A second application in which graphene inclusion would be beneficial is the field of spintronics, in which the spin orientation of electrons are used as an additional degree of freedom for computation and information storage. This beyond-CMOS application represents an avenue for significant improvement over current technologies and graphene, with its weak spin orbit coupling and high electron mobility, displays potential as a long-distance spin transport component of future spintronic devices. Characterization of graphene's spin transport properties has been primarily investigated in a nonlocal spin valve device (NLSV), resulting in experimental spin transport parameters orders of magnitude below those theoretical predicted. To advance graphene as a component for future spintronic applications, new device designs to explore spin transport phenomena not detectable in NLSV devices as well as scalable fabrication techniques will be needed. In this work, we develop graphene synthesis techniques to reduce required temperatures through hydrocarbon precursor control during plasma enhanced chemical vapor deposition (PECVD). Through manipulation of the size and ionization state of hydrocarbon precursors that interact with the growth catalyst, we demonstrate 95% few-to-monolayer graphene synthesis at 500°C on 50 nm catalysts, representing a 10-fold reduction in catalyst thickness requirements at temperatures approaching the limit for direct incorporation in CMOS applications. Additionally, we demonstrate manipulation of metal catalyst morphology and composition toward controlling graphene layer