Development of coaxial shield via in silicon carrier for high frequency application

Abstract

System-in-package (SiP) based on silicon carriers is a fast emerging technology that offers system design flexibility and integration of heterogeneous technologies. One of the key technologies enabler for silicon carrier is through wafer interconnects. The development of SiP will require the devices with different functionality operating at high frequency to be densely packed on the silicon substrate. However, silicon substrate is usually of low resistivity, when a high frequency signal is transmitted vertically through the substrate via, significant signal attenuation can occur that leads to substrate crosstalk and poor RF performance. In this paper, a novel coaxial shielded via in silicon carrier is presented for high frequency applications. Electrical modeling was carried out to obtain the required geometries for optimum performance. The coaxial shield via is able to suppress undesirable substrate crosstalk between vertical interconnects as well as provide excellent RF performance. The detailed fabrication process is also presented. A negative tone SU-8 photoresist is used as the dielectric for the coaxial shield via structure. A test vehicle is fabricated on 8-inch, 10 Omegamiddotcm resistivity silicon wafer with a target of achieving a transmission coefficient, S21 of greater than -0.5 dB at 40 GHz. SU-8 dielectric of approximately 112 mum thickness was deposited on the via sidewall of a 300 mum diameter through wafer via holes, and the via-holes filled with copper using bottom up electroplating approach to achieve a radius ratio, n of 4