Development of Automation Tool for Optimising Floorplan of a Given VLSI Design

Abstract

With the advancement in technology, the design complexity has increased rapidly because of ever increasing chip density. So VLSI physical design needs to be optimized. Floorplanning is the first step for the Physical Design Flow which determines the locations as well as the dimensions of the components in a chip so as to optimize the chip area and wire length. Simulated Annealing algorithm is considered for optimizing the initial floorplan. The concept of Simulated Annealing has been used to develop a method to obtain the optimized floorplan. The cost function used in this algorithm is weighted sum of the normalized area, wire length and overlap. It employs random moves on the modules to generate new configuration of the floorplan and then it checks whether the cost function of that configuration is reduced. It accepts those moves and rejects the remaining. The input file consists of modules, terminals and netlists which is used to obtain the layout of the floorpolan. The area of the modules has been found. The schematic of the module is first designed and simulated and a verilog file is generated which is compiled to extract the transistor-level design (based on 120 nm CMOS technology) which gives the area.User interactive Java applet has been developed to display the layout of the floorplan. Accepted and reject moves were displayed for a point in the temperature and the cost vs temperature schedule is generated to verify the simulated annealing process. The final optimized floorplan is obtained after reaching the temperature having the globally optimum cost. The improvement in the area, wire length, overlap and the cost can be observed when compared to the initial floorplan.