Development of an Abrasive Embedded Pad for Dishing Reduction and Uniformity Enhancement

Abstract

Chemical mechanical polishing (CMP) has been widely accepted for the planarization of multilayer structures in semiconductor manufacturing. CMP is optimized by several process parameters, such as the equipment, pad, and slurry. However, there have been serious problems in CMP in terms of repeatability and defects in patterned wafers. Especially, dishing & erosion defects increase the resistance because they decrease the interconnect section area, and ultimately reduce the lifetime of the semiconductor. Methods to reduce dishing & erosion have recently been introduced: minimizing the abrasive concentration, minimizing the oxidizer volume, increasing the surface hardness of the pad, optimization of the pattern structure as dummy patterns. However, minimizing the oxidizer and increasing the pad hardness are concerned with the removal rate and the quality of the polished wafer. Therefore, minimizing the abrasive concentration by using CeO2 is the best solution for reducing dishing & erosion. The removal rate can be maintained because a CeO2 abrasive has good polishing characteristics compared with SiO2. This paper introduces a dishing & erosion generating mechanism and a method for developing a semi-rigid abrasive pad to minimize dishing & erosion during CMP. Dishing & erosion are initially generated by an uneven pressure distribution in the materials. These defects are accelerated by free abrasives and chemical etching. Therefore, it is known that dishing & erosion can be reduced by minimizing the abrasive concentration. The developed semi-rigid abrasive pad was applied to Interlayer dielectric (ILD) CMP, and the result was compared with that of a conventional pad in terms of material removal rate, within wafer non-uniformity, and surface damage.