Development of a readout electronic prototype system for the MWDC at the ETF in HIRFL-CSR

Abstract

This paper proposes and implements a readout electronic prototype system for a Multi-Wire Drift Chamber (MWDC) detector. This system includes Front-End Electronics (FEE), Sub_Data Acquisition (Sub_DAQ), and Common Data Acquisition Unit (CDAU). Based on a self-developed Application-Specific Integrated Circuit (ASIC) chip, the FEE amplifies and reshapes the detector signals before transmitting them via a high-density micro-coaxial cable to the Sub_DAQ. The Sub_DAQ, based on a Field-Programmable Gate Array (FPGA), was designed to process MWDC signals. The Sub_DAQ can perform an analogue-to-digital conversion, online data processing, and package transmission before transmitting the data to the CDAU via a high-speed optical fibre link. The CDAU gathered data, online processed the data, and then transmitted the data to the computer via the PCIe 3.0 interface. This paper will discuss the design process, the implementation, and the initial test results of the readout electronic prototype system.